A programmable logic device (hereinafter also referred to as a PLD) is a semiconductor integrated circuit capable of rewriting its circuit configuration after the chip manufacturing, and a typical example of such a PLD is a field programmable gate array (hereinafter also referred to as an FPGA). An island-style PLD has a two-dimensionally repetitive configuration in which a configurable logic block and a configurable memory block are connected to each other by a configurable interconnect block. Each configurable memory block is preferably capable of supplying data to the corresponding configurable logic block at a higher data rate (bits/sec). The data rate is determined by the product of the data transfer clock frequency fclk and the data bit width W. The data transfer clock speed is normally limited by the maximum read clock frequency of the memory core included in the configurable memory block. Meanwhile, the data bit width is limited by the number of I/Os in the configurable block connecting the configurable memory block and the configurable interconnect block. Each of the I/Os in the configurable block has a large area due to the configurability thereof, and an increase in the number of I/Os causes a significant increase in area.